The present invention relates to semiconductor memory devices and a method of fabricating the same and, more particularly, to semiconductor memory devices and a method of fabricating the same, in which threshold voltage distributions of semiconductor memory cells can be improved.
A flash memory cell of semiconductor memory devices has a structure in which a tunnel oxide layer, a conductive layer for a floating gate, a dielectric layer, and a conductive layer for a control gate are sequentially stacked over a semiconductor substrate. Program and erase operations of the flash memory cell are performed by injecting or draining electrons into or from the conductive layer for the floating gate.
FIG. 1 is a sectional view illustrating a conventional method of fabricating a semiconductor memory device.
Referring to FIG. 1, a tunnel oxide layer 11 and a polysiliocn layer 12 for a floating gate are formed over a semiconductor substrate 10. The polysiliocn layer 12 and the tunnel oxide layer 11 are selectively etched to thereby expose an isolation region of the semiconductor substrate 10. Then, a trench 13 is formed by etching the exposed semiconductor substrate 10. The trench 13 is gap-filled with an insulating layer, thus forming an isolation layer 14.
Although not shown in the drawing, a dielectric layer and a conductive layer for a control gate are sequentially stacked on the entire surface including the isolation layer 14, thus forming a semiconductor memory device.
When a program operation is performed on the conventional semiconductor memory device, program threshold voltages of respective memory cells differ, thereby forming a distribution in program threshold voltages. This is caused by traps included in the insulating layer near the floating gate. The traps are irregular due to the grains of polycrystalline silicon at the boundary of the conductive layer for the floating gate and the insulating layer. Phosphorous (P) ions, injected into the conductive layer for the floating gate, are distributed in large quantities at the boundary region of the insulating layer and the conductive layer for the floating gate which has large grains. It has an influence on the characteristics of the insulating layer such as a tunnel oxide layer, which comes in contact with the conductive layer for the floating gate.
If a program threshold voltage distribution of a memory cell is widened, device characteristics and uniformity are degraded. It results in significant low margin and decreased reliability of devices, particularly in a device having a narrow cell distribution margin such as a multi-level cell (MLC).